open-source-eda

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

OpenRule1umPDKを各種環境にセットアップするためのスクリプトです。

Traceable datasheet-to-SPICE model generation for power MOSFETs and diodes, with browser extraction and validation benchmarks.

Agentic, evidence-driven Spec-to-RTL-to-GDS workflow with verified RTL and managed LibreLane implementation

Open-source MBIST generator for OpenRAM SRAM macros with built-in BIRA/BISR redundancy repair, plus a programmable march-algorithm fault-model research platform

4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground

This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.

SHA-256 accelerator on Caravel SoC (SkyWater 130nm) - open-source RTL-to-GDSII signoff flow

A curated list of semiconductor industry resources, with a deliberate bias toward sub-10nm logic, lithography, process technology, and advanced packaging.

A decode-phase KV-cache engine for LLM inference: SystemVerilog RTL to a sign-off-clean GDSII on SkyWater 130nm (0 DRC, 0 LVS, timing closed), with a formally proved paged allocator and a 16-node sequence-parallel mesh over a torus NoC.

A hands-on implementation of physical design for a Serial Peripheral Interface (SPI) controller — progressing from RTL Verilog through synthesis, placement, static timing analysis, routing, DRC, LVS, and GDSII generation using the open-source Qflow EDA toolchain with OSU018 standard cell library.

Parameterized asynchronous CDC FIFO IP: gray-code pointers, a sweepable N-flop synchronizer, IEEE 1801 UPF low-power intent, SymbiYosys formal proofs, and a 60-config Yosys/OpenSTA PPA sweep on SkyWater Sky130. Fully open-source and reproducible.

RTL-to-GDSII physical design flow of PicoRV32a RISC-V processor using OpenLANE and Sky130 PDK. Completed under NASSCOM FutureSkills Prime program. Synthesis, floorplan, placement, CTS, routing, DRC/LVS clean, GDSII generated.

Open-source, modular simulator for optical communication links and photonic systems. Design phase — architecture under review.

Complete RTL-to-GDSII physical design flow of an 8-bit ALU using OpenLane and Sky130 PDK. Includes synthesis, floorplanning, placement, CTS, routing, DRC/LVS signoff, and multi-corner STA.

int8 serial multiply accumulate for Tiny Tapeout sky130, RTL to GDS on open tools, mutation gated formal proof, one hash sealed

RTL-to-GDS physical design of a parameterized MAC accelerator using open-source ASIC tools (Yosys, OpenLane, Sky130)